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november 25, 1997 (version 1.1) 5-11 features ? extended family of one-time programmable (otp) bit-serial read-only memories used for storing the con?guration bitstreams of xilinx fpgas ? on-chip address counter, incremented by each rising edge on the clock input ? simple interface to the fpga requires only one user i/o pin ? cascadable for storing longer or multiple bitstreams ? programmable reset polarity (active high or active low) for compatibility with different fpga solutions ? xc17128d or xc17256d supports xc4000 fast con?guration mode (12.5 mhz) ? low-power cmos eprom process ? available in 5 v and 3.3 v versions ? available in plastic and ceramic packages, and commercial, industrial and military temperature ranges ? space ef?cient 8-pin dip, 8-pin soic, 8-pin voic, or 20-pin surface-mount packages. ? programming support by leading programmer manufacturers. description the xc1700 family of serial con?guration proms (scps) provides an easy-to-use, cost-effective method for storing xilinx fpga con?guration bitstreams. when the fpga is in master serial mode, it generates a con?guration clock that drives the scp. a short access time after the rising clock edge, data appears on the scp data output pin that is connected to the fpga din pin. the fpga generates the appropriate number of clock pulses to complete the con?guration. once con?gured, it disables the scp. when the fpga is in slave mode, the scp and the fpga must both be clocked by an incoming signal. multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all scps in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family. for device programming, the xact development system compiles the fpga design ?le into a standard hex format, which is then transferred to the programmer. 0 xc1700d family of serial con?guration proms november 25, 1997 (version 1.1) 05* product specification a figure 1: simpli?ed block diagram (does not show programming circuit) eprom cell matrix address counter ce reset/ oe or oe/ reset data ceo oe output clk v cc v pp gnd x3185 tc
xc1700d family of serial con?guration proms 5-12 november 25, 1997 (version 1.1) pin description data data output, 3-stated when either ce or oe are inactive. during programming, the data pin is i/o. note that oe can be programmed to be either active high or active low. clk each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/ oe when high, this input holds the address counter reset and 3-states the data output. the polarity of this input pin is programmable as either reset/ oe or oe/ reset. to avoid confusion, this document describes the pin as reset/ oe, although the opposite polarity is possible on all devices. when reset is active, the address counter is held at zero, and the data output is 3-stated. the polarity of this input is programmable. the default is active high reset, but the preferred option is active low reset, because it can be driven by the fpgas init pin. the polarity of this pin is controlled in the programmer inter- face. this input pin is easily inverted using the xilinx hw- 130 programmer software. third-party programmers have different methods to invert this pin. ce when high, this pin disables the internal address counter, 3-states the data output, and forces the device into low-i cc standby mode. ceo chip enable output, to be connected to the ce input of the next scp in the daisy chain. this output is low when the ce and oe inputs are both active and the internal address counter has been incremented beyond its terminal count (tc) value. in other words: when the prom has been read, ceo will follow ce as long as oe is active. when oe goes inactive, ceo stays high until the prom is reset. note that oe can be programmed to be either active high or active low. v pp programming voltage. no overshoot above the speci?ed max voltage is permitted on this pin. for normal read oper- ation, this pin must be connected to v cc . failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. do not leave vpp ?oating! v cc and gnd v cc is positive supply pin and gnd is ground pin. serial prom pinouts capacity pin name 8-pin 20-pin data 1 2 clk 2 4 reset/ oe (oe/ reset) 3 6 ce 4 8 gnd 5 10 ceo 6 14 v pp 717 v cc 820 device con?guration bits xc1718d or l 18,144 xc1736d 36,288 xc1765d or l 65,536 xc17128d or l xc17256d or l 131,072 262,144 xc17512l 524,288 xc1701 or l 1,048,576
november 25, 1997 (version 1.1) 5-13 number of con?guration bits, including header for all xilinx fpgas and compatible scp type controlling serial proms most connections between the fpga device and the serial prom are simple and self-explanatory. ? the data output(s) of the of the serial prom(s) drives the din input of the lead fpga device. ? the master fpga cclk output drives the clk input(s) of the serial prom(s). ? the ceo output of a serial prom drives the ce input of the next serial prom in a daisy chain (if any). ? the reset/oe input of all serial proms is best driven by the init output of the xc3000 or xc4000 lead fpga device. this connection assures that the serial prom address counter is reset before the start of any (re)con?guration, even when a recon?guration is initiated by a v cc glitch. other methods C such as driving reset/oe from ldc or system reset C assume that the serial prom internal power-on-reset is always in step with the fpgas internal power-on-reset, which may not be a safe assumption. ? the ce input of the lead (or only) serial prom is driven by the done/ prgm or done output of the lead fpga device, provided that done/ prgm is not permanently grounded. otherwise, ldc can be used to drive ce, but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. fpga master serial mode summary the i/o and logic functions of the logic cell array and their associated interconnections are established by a con?gu- ration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master mode, the fpga automatically loads the con?guration program from an external memory. the serial con?guration prom has been designed for compatibility with the master serial mode. upon power-up or recon?guration, an fpga enters the master serial mode whenever all three of the fpga mode- select pins are low (m0=0, m1=0, m2=0). data is read from the serial con?guration prom sequentially on a single data line. synchronization is provided by the rising edge of the temporary signal cclk, which is generated during con- ?guration. master serial mode provides a simple con?guration inter- face. only a serial data line and two control lines are required to con?gure an fpga. data from the serial con- ?guration prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function din pin on the fpga is used only for con?guration, it must still be held at a de?ned level during normal operation. the xc3000 and xc4000 families take care of this automatically with an on- chip default pull-up resistor. with xc2000-family devices, the user must either con?gure din as an active output, or provide a de?ned level, e.g., by using an external pull-up resistor, if din is con?gured as an input. programming the fpga with counters unchanged upon completion when multiple fpga-con?gurations for a single fpga are stored in a serial con?guration prom, the oe pin should be tied low. upon power-up, the internal address counters are reset and con?guration begins with the ?rst program stored in memory. since the oe pin is held low, the address counters are left unchanged after con?guration is complete. therefore, to reprogram the fpga with another program, the d/ p line is pulled low and con?guration begins at the last value of the address counters. device con?guration bits scp xc3x20a/l 14,819 xc1718d xc3x30a/l 22,216 xc1736d xc3x42a/l 30,824 xc1736d xc3x64a/l 46,104 xc1765d xc3x90a/l 64,200 xc1765d xc3195a 94,984 xc17128d xc4003e 53,984 xc1765d xc4005e 95,008 xc17128d/l xc4006e 119,840 xc17128d xc4008e 147,552 xc17256d xc4010e 178,144 xc17256d/l xc4013e 247,968 xc17256d/l xc4020e 329,312 xc1701 xc4025e 422,176 xc1701 xc4005xl 151,960 xc17256l xc4010xl 283,424 xc17512l xc4013xl 393,623 xc17512l xc4020xl 521,880 xc17512l xc4028ex/xl 668,184 xc1701l xc4036ex/xl 832,528 xc1701l xc4044xl 1,014,928 xc1701l xc4052xl 1,215,368 xc1701l + xc17256l xc4062xl 1,433,864 xc1701l + xc17512l xc4085xl 1,924,992 2 xc1701l xc5202 42,416 xc1765d xc5204 70,704 xc17128d xc5206 106,288 xc17128d xc5210 165,488 xc17256d xc5215 237,744 xc17256d
xc1700d family of serial con?guration proms 5-14 november 25, 1997 (version 1.1) this method fails if a user applies reset during the fpga con?guration process. the fpga aborts the con?guration and then restarts a new con?guration, as intended, but the serial prom does not reset its address counter, since it never saw a high level on its oe input. the new con?gura- tion, therefore, reads the remaining data in the prom and interprets it as preamble, length count etc. since the fpga is the master, it issues the necessary number of cclk pulses, up to 16 million (2 24 ) and d/ p goes high. however, the fpga con?guration will be completely wrong, with potential contentions inside the fpga and on its output pins. this method must, therefore, never be used when there is any chance of external reset during con?guration. cascading serial con?guration proms for multiple fpgas con?gured as a daisy-chain, or for future fpgas requiring larger con?guration memories, cas- caded scps provide additional memory. after the last bit from the ?rst scp is read, the next clock signal to the scp asserts its ceo output low and disables its data line. the second scp recognizes the low level on its ce input and enables its data output. see figure 2 . after con?guration is complete, the address counters of all cascaded scps are reset if the fpga reset pin goes low, assuming the scp reset polarity option has been inverted. to reprogram the fpga with another program, the d/ p line goes low and con?guration begins where the address counters had stopped. in this case, avoid contention between data and the con?gured i/o use of din.
november 25, 1997 (version 1.1) 5-15 figure 2: master serial mode. the one-time-programmable serial con?guration prom supports automatic loading of con?guration programs. multiple devices can be cascaded to support additional fpga. an early d/ p inhibits the prom data output one cclk cycle before the fpga i/os become active. * if readback is activated, a 5-k w resistor is required in series with m1 during configuration the 5 k w m2 pull-down resistor overcomes the internal pull-up, but it allows m2 to be user i/o. general- purpose user i/o pins other i/o pins m2 hdc ldc init reset din cclk init d/p scp data ceo clk ce optional slave fpgas with identical configurations +5 v * m0 m1 pwrdwn xc3000 fpga device (low resets the address pointer) +5 v v cc v pp reset x5090 cascaded serial memory data clk ce optional daisy-chained fpgas with different configurations dout cclk (output) din dout (output) oe/reset oe/reset
xc1700d family of serial con?guration proms 5-16 november 25, 1997 (version 1.1) standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high imped- ance state regardless of the state of the oe input. programming the xc1700 family serial proms the devices can be programmed on programmers supplied by xilinx or quali?ed third-party vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. notes: 1. the xc1700 reset input has programmable polarity 2. tc = terminal count = highest address value. tc+1 = address 0. table 1: truth table for xc1700 control inputs control inputs internal address outputs reset ce data ceo i cc inactive low if address < tc: increment if address > tc: dont change active 3-state high low active reduced active low held reset 3-state high active inactive high not changing 3-state high standby active high held reset 3-state high standby
november 25, 1997 (version 1.1) 5-17 xc1718d, xc1736d, xc1765d, xc17128d and xc17256d absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. operating conditions dc characteristics over operating condition note : during normal read operation v pp must be connected to v cc symbol description units v cc supply voltage relative to gnd -0.5 to +7.0 v v pp supply voltage relative to gnd -0.5 to +12.5 v v in input voltage relative to gnd -0.5 to v cc +0.5 v v ts voltage applied to 3-state output -0.5 to v cc +0.5 v t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in.) +260 c symbol description min max units v cc commercial supply voltage relative to gnd 0 c to +70 c junction 4.75 5.25 v industrial supply voltage relative to gnd -40 c to +85 c junction 4.50 5.50 v military supply voltage relative to gnd -55 c to +125 c case 4.50 5.50 v symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = -4 ma) commercial 3.86 v v ol low-level output voltage (i ol = +4 ma) 0.32 v v oh high-level output voltage (i oh = -4 ma) industrial 3.76 v v ol low-level output voltage (i ol = +4 ma) 0.37 v v oh high-level output voltage (i oh = -4 ma) military 3.7 v v ol low-level output voltage (i ol = +4 ma) 0.4 v i cca supply current, active mode 10.0 ma i ccs supply current, standby mode, xc17128d, xc17256d 50.0 m a supply current, standby mode, xc1718d, xc1736d, xc1765d 1.5 ma i l input or output leakage current -10.0 10.0 m a
xc1700d family of serial con?guration proms 5-18 november 25, 1997 (version 1.1) xc1718l, xc1765l, xc17128l and xc17256l absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. operating conditions dc characteristics over operating condition note: during normal read operation v pp must be connected to v cc symbol description units v cc supply voltage relative to gnd -0.5 to +6.0 v v pp supply voltage relative to gnd -0.5 to +12.5 v v in input voltage with respect to gnd -0.5 to v cc +0.5 v v ts voltage applied to 3-state output -0.5 to v cc +0.5 v t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in.) +260 c symbol description min max units v cc commercial supply voltage relative to gnd 0 c to +70 c junction 3.0 3.6 v symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = -4 ma) 2.4 v v ol low-level output voltage (i ol = +4 ma) 0.4 v i cca supply current, active mode 5.0 ma i ccs supply current, standby mode, xc1718l, xc1765l supply current, standby mode, xc17128l, xc17265l 1.5 50.0 ma m a i l input or output leakage current -10.0 10.0 m a
november 25, 1997 (version 1.1) 5-19 ac characteristics over operating condition notes: 1. ac test load = 50 pf 2. float delays are measured with minimum tester ac load and maximum dc load. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0 v and v ih = 3.0 v. reset/oe ce clk data 1 t ce 2 t oe t lc 7 9 t sce t sce t hce t hoe 11 t cac t oh t df 5 t oh 4 4 3 9 10 t hc 8 x2634 t cyc 6 symbol description xc1718d xc1736d xc1765d xc1718l xc1765l xc17128d xc17256d xc17128l xc17256l units min max min max min max min max 1t oe oe to data delay 45 45 25 30 ns 2t ce ce to data delay 60 60 45 60 ns 3t cac clk to data delay 150 200 50 60 ns 4t oh data hold from ce, oe, or clk0000ns 5t df ce or oe to data float delay 2 50 50 50 50 ns 6t cyc clock periods 200 400 80 100 ns 7t lc clk low time 3 100 100 20 25 ns 8 thc clk high time 3 100 100 20 25 ns 9 tsce ce setup time to clk (to guarantee proper counting) 25 40 20 25 ns 10 t hce ce hold time to clk (to guarantee proper counting) 0000ns 11 t hoe oe hold time (guarantees counters are reset) 100 100 20 25 ns
xc1700d family of serial con?guration proms 5-20 november 25, 1997 (version 1.1) ac characteristics over operating condition (continued) notes: 1. ac test load = 50 pf 2. float delays are measured with minimum tester ac load and maximum dc load. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0 v and v ih = 3.0 v. symbol description xc1718d xc1736d xc1765d xc1718l xc1765l xc17128d xc17256d xc17128l xc17256l units min max min max min max min max 12 t cdf clk to data float delay 2 50 50 50 50 ns 13 t ock clk to ceo delay 65 65 30 30 ns 14 t oce ce to ceo delay 45 45 35 35 ns 15 t ooe reset/ oe to ceo delay 40 40 30 30 ns reset/oe clk data ce 15 t ooe ceo first bit last bit t oce 13 t ock 12 t cdf x3183 14 t oce 14
n o v ember 25, 1997 ( v ersion 1.1) 5-21 o r dering in f ormation v alid o r dering combinations marking in f ormation due to the small si z e of the se r ial p r om pa c kag e , the complete orde r ing pa r t n umber cannot be ma r k ed on the pa c kag e . the xc pre?x is deleted and the pa c kage code is simpli?ed. d e vice ma r king is as f oll o w s . xc17128dpd8c xc1718dpd8c xc17256dpd8c xc1736dpd8c xc1765dpd8c xc17128dvo8c xc1718dso8c xc17256dvo8c xc1736dso8c xc1765dso8c xc17128dpc20c xc1718dvo8c xc17256dpc20c xc1736dvo8c xc1765dvo8c xc17128dpd8i xc1718dpc20c xc17256dpd8i xc1736dpc20c xc1765dpc20c xc17128dvo8i xc1718dpd8i xc17256dvo8i xc1736dpd8i xc1765dpd8i XC17128DPC20I xc1718dso8i xc17256dpc20i xc1736dso8i xc1765dso8i xc17128ddd8m xc1718dvo8i xc17256ddd8m xc1736dvo8i xc1765dvo8i xc1718dpc20i xc17256ddd8b xc1736dpc20i xc1765dpc20i xc1736ddd8m xc1765ddd8m xc1765ddd8b xc17128lpd8c xc1718lpd8c xc17256lpd8c xc1765lpd8c xc17128lvo8c xc1718lso8c xc17256lvo8c xc1765lso8c xc17128lpc20c xc1718lvo8c xc17256lpc20c xc1765lvo8c xc17128lpd8i xc1718lpc20c xc17256lpd8i xc1765lpc20c xc17128lvo8i xc1718lpd8i xc17256lvo8i xc1765lpd8i xc17128lpc20i xc1718lso8i xc17256lpc20i xc1765lso8i xc1718lvo8i xc1765lvo8i xc1718lpc20i xc1765lpc20i xc1736d pc20 c operating ran g e/p r ocessing c = commercial (0 to +70 c) i = indust r ial (C40 to +85 c) m = milita r y (C55 to +125 c) b = milita r y (C55 to +125 c) mil-std-883 l e v el b compliant p a c k a g e t ype pd8 = 8-pin plastic dip dd8 = 8-pin cerdip so8 = 8-pin plastic small-outline p a c kage v o8 = 8-pin plastic small-outline thin p a c kage pc2 0 = 20-pin plastic leaded chip car r ier d e vice number xc1718d xc1718l xc1736d xc1765d xc1765l xc17128d xc17128l xc17256d xc17256l 1736d p c operating ran g e/p r ocessing c = commercial (0 to +70 c) i = indust r ial (C40 to +85 c) m = milita r y (C55 to +125 c) b = milita r y (C55 to +125 c) mil-std-883 l e v el b compliant p a c k a g e t ype p = 8-pin plastic dip d = 8-pin cerdip s = 8-pin plastic small-outline p a c kage v = 8-pin plastic small-outline thin p a c kage j = 20-pin plastic leaded chip car r ier d e vice number xc1718d xc1718l xc1736d xc1765d xc1765l xc17128d xc17128l xc17256d xc17256l

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